At the IC World conference in Beijing, Ye Tianchun, chief engineer of China’s National Major Special Project 02, told the audience that IMECAS — the Institute of Microelectronics at the Chinese Academy of Sciences — had completed what he called “early process integration” of a transistor built without the one tool China cannot buy.
DIGITIMES first reported the disclosure on September 17. The device in question is a stacked-nanosheet gate-all-around (GAA) transistor, fabricated entirely with deep ultraviolet (DUV) lithography rather than the extreme ultraviolet (EUV) machines that ASML is barred from selling to Chinese customers under US-led export controls. IMECAS reported on/off current ratios of 9.7×10⁵ and 7.6×10⁵ for its devices, both clearing the 5×10⁵ threshold researchers typically use to confirm that a transistor’s gate is cleanly controlling the channel beneath it.
The announcement moved quickly through the semiconductor press — Tom’s Hardware, TrendForce, Wccftech and others all covered it within days — and for good reason. It is real evidence that Chinese researchers can advance transistor technology along a track that does not depend on Western lithography tools. But nearly every outlet that examined the claim closely reached the same second conclusion: this is a laboratory-stage demonstration of a device structure, not a finished 3-nanometer manufacturing process, and the distance between the two remains large.
Both of those things can be true at once, and understanding why requires unpacking what a transistor “wrapped all the way around” actually buys an engineer, and what an on/off ratio does and does not tell you about a finished chip.
What a Transistor That Wraps All the Way Around Actually Does
Picture a transistor’s channel as a thin bar of silicon that current flows through, controlled by a gate that switches it on and off — like a valve. In FinFET transistors, the design used at most advanced nodes until recently, that gate touches the channel from three sides, like a hand gripping a bar from three directions. It works well, but as transistors shrink, current starts leaking through the side the gate can’t reach, a problem called the short-channel effect.
Gate-all-around, or GAA, closes that gap literally: the gate wraps completely around a thin sheet-shaped channel, like a fist closing all the way around a rod rather than gripping it from three sides. That full contact gives the gate much more complete control over the channel, which is exactly why TSMC, Samsung and Intel have all adopted GAA-family designs at their most advanced current nodes.
IMECAS’s version stacks several of these nanosheet channels on top of each other. By tuning how wide each sheet is and how many layers are stacked, engineers can increase the total channel area — and therefore the current the transistor can drive — without making the transistor take up more space on the chip. It’s a way of adding capacity vertically rather than spreading out horizontally.
The on/off ratio IMECAS reported is best understood the way you’d judge a light switch: how cleanly does it distinguish “fully on” from “fully off,” rather than settling into some dim, ambiguous in-between state? A ratio above 500,000 — which both of IMECAS’s reported figures clear — indicates the gate is doing its job of decisively shutting off current flow when required, which is a meaningful, if narrow, confirmation that the device physics work as designed.
This is not IMECAS’s first pass at the problem. The institute has published peer-reviewed GAA research since 2020, including 2023 papers in IEEE Electron Device Letters describing “FishboneFET” and “TreeFET” structures that increase channel area within a fixed footprint, and a 2025 study showing that a low-temperature ozone treatment applied before gate formation cut interface defects by two orders of magnitude, improved subthreshold swing to 60.3 mV/decade, reduced off-current by 66.7%, and boosted on-current by more than 20%.
Squeezing 3nm-Class Performance Out of Older Lithography
The reason IMECAS is pursuing this path at all comes down to one piece of equipment it cannot buy. EUV lithography machines, made exclusively by the Dutch company ASML, can print the extremely fine patterns modern chips require in a single exposure — something like printing a highly detailed page in one pass through a printer. Export controls led by the United States have kept ASML from selling EUV systems to Chinese chipmakers for years.
DUV, the older lithography technology China does have access to, cannot achieve that same fineness in one pass. Chipmakers work around this with a technique called multi-patterning: breaking a single fine pattern into several separate, overlapping exposures, each requiring its own etching and alignment step — closer to running the same page through a printer several times, carefully realigning it each time, to build up detail a single pass can’t capture.
GAA’s electrical advantages give this workaround more room to succeed. Because wrapping the gate fully around the channel improves control regardless of exactly how small the pattern is, a well-designed GAA structure can potentially deliver strong electrical performance even without pushing DUV to print patterns quite as fine as EUV would need — trading some lithographic precision for a smarter transistor structure.
That tradeoff is not free, though. ASML’s own 2025 annual report estimates, using a generalized imec.netzero model, that DUV multi-patterning requires roughly 20% more process steps per wafer than EUV single patterning. More steps mean more masks, more equipment time, more materials, and more opportunities for the misalignment or defects that hurt manufacturing yield — costs that don’t show up in a single transistor’s on/off ratio but matter enormously for mass production.
IMECAS’s public research portfolio suggests this is a sustained program rather than a one-off stunt: the institute lists work on optical proximity correction, source-mask co-optimization, double patterning, and inverse lithography, spanning process nodes from a relatively mature 45 nanometers down to 3 nanometers — computational and structural techniques aimed specifically at extracting more performance from DUV tools than they were originally designed to deliver.
For a sense of the commercial baseline IMECAS is chasing, see our earlier coverage of TSMC’s revenue running ahead of its own guidance — a reminder of how far ahead the incumbent EUV-based leaders already are in output and demand.
The Gap Between a Working Transistor and a Finished Chip
Here is what IMECAS has not disclosed, and it matters: gate pitch, metal pitch, nanosheet dimensions, transistor density, and SRAM density — the geometric figures that would let anyone actually compare this device to a real 3nm-class node from TSMC, Samsung Foundry or Intel. Without them, “3nm-class” describes an ambition and a research direction more than a measured result.
A transistor-density figure of 137.8 million transistors per square millimeter, compared favorably in some coverage to “TSMC’s 5nm-class” density, circulated widely after the announcement. It did not come from CAS or China’s SMIC. Independent analysis by XenoSpectrum traced it to an estimate posted by an account on X, based on assumed standard-cell dimensions rather than measured or disclosed data — the kind of number that looks precise but cannot be verified against anything the researchers themselves published.
An on/off ratio alone also doesn’t reveal switching speed, operating voltage, or how much current the transistor can drive per unit of width — the figures that actually determine whether a chip built from these transistors would be fast or power-efficient enough to be commercially competitive. A device can post an excellent on/off ratio while still falling well short of what a production node requires on these other measures.
Building one working transistor is also only the first stage of many. Connecting billions of them into a functioning chip requires middle- and back-end-of-line processes — contacts, and layers of metal wiring — that introduce their own resistance, capacitance, and alignment challenges as dimensions shrink. IMECAS’s demonstration addresses the transistor itself; it says nothing yet about how these interconnects would perform at the same scale.
For a sense of what a complete, verified dataset looks like, consider how Samsung described its first 3nm GAA node when it began mass production in 2022: up to 45% lower power consumption at equivalent performance and complexity versus its own 5nm process, up to 23% higher performance at equivalent power, or up to 16% smaller chip area at equivalent design — a full power-performance-area comparison Samsung was able to back with real manufacturing data. IMECAS has not yet published anything at that level of completeness.
Taken together, the outlets that reviewed the claim converged on roughly the same verdict: this is genuine, meaningful evidence that China can chart an independent path in transistor technology without leading-edge Western lithography tools — a capability with real strategic weight given the export restrictions it is designed to work around. But a production-ready Chinese 3nm-class node “remains distant,” in the words of one review, with outside estimates suggesting it is still years away rather than an imminent alternative to TSMC’s or Samsung’s advanced nodes.
References
DIGITIMES, “Exclusive: China’s CAS institute charts DUV route to 3nm GAA without EUV,” September 17, 2026
Tom’s Hardware, “China crafts working 3nm gate-all-around transistors without EUV,” September 21, 2026 (Anton Shilov)
XenoSpectrum, “China’s 3nm-Class GAA Transistor Claim: What a 500,000 On-Off Ratio Actually Proves,” September 19, 2026
TrendForce, “Chinese Researchers Reportedly Push GAA With DUV, Opening Potential Path to 3nm-Level Performance,” September 18, 2026
