For roughly fifteen years, the question that organised the chip industry was simple: whose processor is fastest. Everything else — memory, packaging, cooling, networking — was a supporting cast arranged around that one contest.
SEMICON Taiwan 2026, which opened its forum programme in Taipei on Monday, August 31, is built around a different question. Almost every session this week is, in one way or another, about whether the wires between chips can keep up with the chips themselves.
Terry Tsao, SEMI’s global chief marketing officer and president for Taiwan, put it in one sentence at the event: data movement in today’s AI systems could consume more energy than computation itself, which makes system architecture, not individual chip performance, the new bottleneck.
Why Copper Stopped Scaling
The physics behind that sentence is not exotic, and it is worth understanding because it explains the entire week’s agenda.
A large AI cluster today has to shuttle data between thousands of accelerators, switches and memory systems at rates exceeding 100 terabits per second per node. Copper can carry that, but not for free and not for long.
Electrical signalling over copper degrades with distance, so the receiving end needs equalisation and retiming circuits to reconstruct a clean signal. The power those circuits draw scales with the data rate, which means the faster you push copper, the larger the fraction of your power budget goes to fixing the wire rather than doing work.
Past a certain speed, adding compute stops helping. The heat generated by moving data grows faster than the performance you gain by adding another accelerator to feed.
A useful way to picture it: a warehouse can hire more packers, but if the loading dock and the road outside stay the same width, the extra packers only make the queue longer. AI clusters reached that point on the road, not in the warehouse.
Co-packaged optics, or CPO, is the industry’s answer. Instead of converting electrical signals to light at a pluggable module on the front panel of a switch — several centimetres of copper trace away — CPO puts the optical engine inside the same package as the switch chip itself.
The electrical path shrinks from centimetres to millimetres. That single geometric change removes most of the equalisation burden, and with it most of the power penalty, while raising the bandwidth that can be squeezed through a given amount of package edge.
Light also does not care about distance the way copper does. Once a signal is photons in a fibre, carrying it to the next rack costs almost nothing extra, which is precisely the problem AI clusters have.
The Year the Slide Became a Purchase Order
CPO has appeared on industry roadmaps for the better part of a decade. What makes 2026 different is that it stopped being a roadmap item and became a manufacturing question, with delivery dates attached.
TSMC’s Compact Universal Photonic Engine platform, known as COUPE, entered mass production this year, alongside a COUPE-on-Substrate variant aimed at CPO switch packages. At a Silicon Photonics Industry Alliance forum in April, TSMC identified the three areas that decide whether the technology scales: wafer-level testing, fibre array units, and high-speed optical packaging assembly.
Those three are not incidental. Testing a photonic wafer means measuring light, not voltage, which requires equipment most fabs did not own five years ago. Fibre array units are the physical problem of aligning glass strands to on-chip waveguides within submicron tolerances, at volume, without a human doing it.
The supplier list assembling behind that platform is what makes the shift look real. Nvidia has partnered with TSMC on COUPE and has begun shipping next-generation Spectrum-X switches using CPO, with the ramp expected in the second half of this year.
Broadcom has started initial deliveries of its 51.2-terabit Bailly CPO switch. TrendForce concluded from those two data points that the technology has entered mass production rather than pilot deployment.
Taiwan’s supply chain has moved in step. United Microelectronics completed its first mass-produced silicon photonics wafers at its Singapore fab with partner Silith Technology, and GlobalWafers brought some silicon photonics products into volume production earlier this year.
Hon Hai expects to begin CPO switch shipments in the third quarter, and its affiliate ShunSin Technology says it has reached mass production capability for both 51.2-terabit and 102.4-terabit CPO products through a TSMC collaboration.
Powertech Technology, working with Broadcom, plans low-volume production of optical engine components this year before integrating them into complete switches in 2027. Largan Precision is preparing a trial run of its first automated CPO line after winning a fibre-array order, and ASE is building out a CPO ecosystem around its VIPack packaging platform.
The programme structure at SEMICON Taiwan reflects that maturity. This year the Silicon Photonics Global Summit ran as a standalone event for the first time, co-chaired by K.C. Hsu, TSMC’s vice president of advanced packaging technology development, and Dr. C.P. Hung, vice president of corporate research and development at ASE.
Cisco opened it on connectivity scaling, TSMC’s Ming Fa Chen presented COUPE, and Lumentum, Marvell, UMC, Lightmatter, imec, Soitec, Lam Research, Onto Innovation, ficonTEC, Advantest and ENLI each took a layer of the manufacturing stack. When an industry gives a technology its own summit and fills every slot with a different production step, the argument about whether it works is over.
The Fight That Comes After the Physics
Winning the physics argument is not the same as winning the deployment argument, and the objection that will define the next two years has nothing to do with bandwidth.
It is serviceability. A pluggable transceiver is designed to be replaced by a technician who walks to the rack, pulls the failed module out of the front panel and pushes a new one in. Field data from hyperscale operators consistently places laser sources among the top failure modes in optical systems, so this is not a theoretical convenience.
Move the optics inside the switch package and that repair path disappears. A failed engine may mean swapping an entire sled and returning it to the vendor, which turns a five-minute fix into a logistics operation.
The industry’s working answer is to split the difference by keeping the lasers outside. External laser sources sit in front-panel modules that remain hot-swappable and thermally controlled, while the modulators and detectors move into the package. Lasers dislike heat, and the inside of a switch package next to a running ASIC is one of the least hospitable places to put one.
The scale of money behind these decisions explains the urgency. SEMI data cited at the show put global semiconductor manufacturing equipment sales at 135.1 billion dollars, up 15 percent year on year.
Its separate 300mm fab outlook projects equipment spending of 133 billion dollars this year and 151 billion in 2027 — the first year the industry will cross 150 billion — rising to 155 billion in 2028 and 172 billion in 2029. SEMI chief executive Ajit Manocha has described this as AI resetting the scale of semiconductor manufacturing investment.
Memory is being pulled into the same reframing. The Memory Executive Summit opened with the argument that memory is no longer defined by capacity alone but by how early and how deeply it is integrated into system design, with global semiconductor revenue expected to approach 975 billion dollars this year and memory alone exceeding 440 billion.
Google’s Amin Vahdat, senior vice president and chief technologist for AI and infrastructure, delivers the CEO Summit keynote on Wednesday — his first public keynote in Asia — on custom silicon, data centres and high-speed networks. The event runs to a record 1,300 exhibitors and more than 100,000 attendees from 65 countries.
The startup floor tells the same story in miniature. The Silicon Startups Zone features Ayar Labs on optical input and output for large AI systems and Neurophos on optical processing units for inference, alongside Quantum Motion on silicon spin qubits built with standard CMOS processes.
What is worth taking from this week is not any single company’s milestone. It is that the constraint on AI has moved twice in three years — first from algorithms to compute, and now from compute to the cost of moving a bit from one place to another.
Every technology dominating this year’s agenda, from silicon photonics to fan-out panel-level packaging to three-dimensional stacking, is a different answer to that same question. The chips are no longer waiting on themselves. They are waiting on the wires, and 2026 is the year the industry started replacing the wires with light.
References
- Oscar Lazenby, “SEMICON Taiwan 2026 Kicks Off: AI Chips’ Bottleneck Is Wires Connecting Them,” Tech Times, August 31, 2026.
- “Semicon to put spotlight on CPO, silicon photonics,” Taipei Times / CNA, August 31, 2026.
- SEMI, “SEMICON Taiwan 2026 to Serve as Global Stage Where the Semiconductor Industry Defines What’s Next,” August 2026.
- SEMI, 300mm Fab Outlook to 2029, April 2026.
- TrendForce, assessment of Nvidia Spectrum-X and Broadcom Bailly CPO shipments, 2026.
- EDN Asia, “SEMICON Taiwan 2026 spotlights breakthroughs in design, memory and optical interconnect.”
- Senko Advanced Components, “The Real Barriers to Co-Packaged Optics: Yield, Reliability, and Serviceability Challenges.”
- SEMICON Taiwan 2026 official forum programme, semicontaiwan.org.
