English translation of the original Korean article: 데이터 속도까지 읽어내는 ‘카멜레온 AI 반도체’, KAIST가 열었다
When a self-driving car navigates a road, the information it must process arrives at wildly different speeds. A pedestrian who suddenly steps into the street, or a car braking hard up ahead, demands a reaction within tens of milliseconds, while changes in road surface or weather unfold over minutes. Wearable devices face a similar mismatch: heart rate shifts from moment to moment, while activity trends change far more slowly.
The trouble is that today’s AI chips are largely blind to these differences in speed. Once a chip is fabricated, its response speed and how long it retains information are fixed, making it hard to handle fast and slow signals well at the same time. That burden has fallen on software instead, driving up both computation and power consumption.
A research team led by Distinguished Professor Choi Sung-Yool of KAIST’s School of Electrical Engineering and Graduate School of Semiconductor Engineering has proposed a different answer. According to research KAIST released on August 7, the team developed a device called a Programmable Dynamic Memtransistor (PDM) — a chip that can program its own response speed and remember that setting. The findings were published in the July issue of Nature Communications.
A memtransistor is a next-generation semiconductor that combines the functions of memory, which stores information, and a transistor, which performs computation, into a single device. The KAIST team went a step further, embedding both a “charge storage layer” that processes data and an “electron trapping layer” that governs response speed into one transistor.
When data comes in, the charge storage layer processes it, while the electron trapping layer adjusts — in multiple steps — how quickly the chip returns to its original state. Much like a chameleon changing color to match its surroundings, the chip adapts its response speed to the speed of incoming data, which is why the team calls it a “chameleon AI semiconductor.”
Concept diagram of the Programmable Dynamic Memtransistor (PDM). By combining a charge storage layer and an electron trapping layer in a single transistor, the device can be programmed across multiple stages to match its response characteristics to the speed of incoming data. Image: courtesy of KAIST.
The experimental results are concrete. The team was able to freely tune the chip’s recovery time by roughly a factor of five, and its characteristic frequency by more than a factor of ten. In an experiment predicting time-series data that mixed fast- and slow-changing information, the device cut prediction error by up to 40 times compared with conventional devices whose response speed is fixed.
The team also built and tested an array connecting multiple PDMs together. It maintained accuracy comparable to existing software-based AI systems while operating on far less energy.
Two features stand out for real-world use: once a response speed is set, it stays in place without any additional power supply, and the device is compatible with CMOS, the process already used in commercial semiconductor manufacturing. That means it could, in principle, be built on existing fabrication lines without new materials or specialized equipment.
The paper’s first author is Kim Dae-won, a PhD student at KAIST’s Graduate School of Semiconductor Engineering; researcher Oh Young-taek and Fellow Lee Jae-duk of Samsung Electronics’ Advanced Institute of Technology also contributed as co-authors. Professor Choi said the work “shows that data changing at a variety of speeds can be processed efficiently without complex separate preprocessing,” adding that it could be applied to fields such as biosignal analysis in wearable devices, dynamic environment recognition in autonomous-driving systems, and real-time sensor processing in robotics.
The achievement connects to a broader trend in that it breaks the long-standing assumption that a chip’s response speed has to be fixed. Research institutions in Korea and abroad have recently poured effort into in-memory computing, which merges memory and computation so data is processed right where it is stored, and into on-device AI chips that process AI locally rather than relying on the cloud. The PDM adds another axis to that picture: a programmable response over time.
To be clear, this remains a laboratory-scale device and array. Turning it into an actual commercial chip will require further steps, including optimizing mass-production processes and validating reliability. Still, its compatibility with the CMOS process is seen as a favorable condition for closing that gap.
The research was supported by the Ministry of Science and ICT’s national R&D program, an ETRI R&D support project, the Ministry of Trade, Industry and Energy’s workforce-development program, and Samsung Electronics.
References
- KAIST, “KAIST develops ‘chameleon AI semiconductor’ with programmable response speeds,” EurekAlert!, Aug. 6, 2026
- Kim, D. et al., “Programmable memtransistor array with temporal dynamics modulation for efficient time-series data processing,” Nature Communications, July 2026
- Lee Jun-gi, “Data Speed-Matched Memory and Computation Simultaneously… Next-Gen AI Semiconductor Device Realized,” Digital Times, Aug. 9, 2026 (Korean)
